120x120mm large chips, with 12 HBM4E stacks.

Do you think AMD's Instinct MI300X and Nvidia's B200 are large-area GPUs? Think again: TSMC is developing a version of its Chip on Wafer on Substrate (CoWoS) packaging technology that will enable system-in-package (SiP) to be more than double in size, the company announced at its North America Technology Symposium. These will use 120x120mm giant packages and will consume several kilowatts of power.

The latest version of CoWoS allows TSMC to build silicon interposers that are about 3.3 times the size of conventional photomask dimensions (858mm^2). As a result, logic circuits, 8 HBM3/HBM3E memory stacks, I/O, and other small chips can occupy up to 2831mm^2 of area. AMD's Instinct MI300X and Nvidia's B200 use this technology, although Nvidia's B200 processor is larger than AMD's MI300X.

The next-generation CoWoS_L, to be produced in 2026, will be able to achieve an interposer size about 5.5 times the cross-sectional size (which may not be as impressive as the 6 times cross-sectional size announced last year). This means 4719 mm^2 will be available for logic, up to 12 HBM memory stacks, and other small chips. Such SiP will also require a larger substrate, and according to TSMC's slides, we are looking at 100x100mm. Therefore, processors of this kind will not be able to use OAM modules.

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TSMC will not stop there; by 2027, it will have a new version of the CoWoS technology that will enable the interposer layer to be 8 times or more in size, which will allow for 6864 square millimeters of space for small chips. One of the designs TSMC envisions relies on four stacked system-on-chip integrated circuits (SoIC) paired with 12 HBM4 memory stacks and additional I/O chips. Such a giant will undoubtedly consume a lot of power—we are talking several kilowatts here, requiring very sophisticated cooling technology. TSMC also hopes that such solutions will use 120x120mm substrates.

Interestingly, earlier this year, Broadcom showcased a custom AI processor with two logic chips and 12 HBM memory stacks. We do not have the specifications for this, but it appears to be larger than AMD's Instinct MI300X and Nvidia's B200, although not as large as TSMC's 2027 plans.Introduction to CoWoS Structure and Technology Classification

CoWoS (Chip On Wafer On Substrate) is a 2.5D advanced packaging technology by TSMC, which is a combination of CoW and oS:

Firstly, the chip is connected to the silicon wafer through the Chip on Wafer (CoW) packaging process, and then the CoW chip is connected with the substrate to form CoWoS. The core is to stack different chips on the same silicon interposer to achieve interconnection of multiple chips. In the silicon interposer, TSMC uses technologies such as micro-bumps (µBumps) and Through-Silicon Vias (TSVs), replacing traditional wire bonding for die-to-die connections, which greatly increases the interconnection density and data transfer bandwidth. CoWoS technology can improve system performance, reduce power consumption, and reduce packaging size, and it also lays the foundation for TSMC to maintain a leading position in subsequent packaging technologies.

Based on the different interlayers used, TSMC classifies the CoWoS packaging technology into three types: CoWoS-S, CoWoS-R, and CoWoS-L.

CoWoS-S (Silicon Interposer) is the advanced packaging technology that first appeared in 2011, using a silicon (Si) substrate as the interlayer (chip-on-wafer-on-substrate with silicon interposer), offering a wide range of interlayer sizes, HBM cube quantities, and packaging sizes. It can achieve a die size greater than 2X (1,700mm²), and the interlayer integrates leading SoC chips and more than four HBM2/HBM2E cubes. In the past, "CoWoS" generally referred to the advanced packaging technology with a silicon substrate as the interlayer.

CoWoS-S has been upgraded from the first generation in 2011 to the fifth generation in 2021, and the sixth-generation technology is expected to be launched in 2023, which will package two computing cores on the substrate and can carry up to 12 HBM memory chips on the board. The fifth-generation CoWoS-S technology uses a brand-new TSV solution, thicker copper interconnections, and the number of transistors is 20 times that of the third generation. Its silicon interlayer has expanded to 2500mm², equivalent to three times the die area, with space for 8 HBM2E stacks, with a capacity of up to 128 GB. Moreover, TSMC provides the latest high-performance processor thermal solution in the form of Metal Tim, which reduces the packaging thermal resistance to 0.15 times compared to the first-generation Gel TIM.

CoWoS-R (RDL Interposer) is an advanced packaging technology that replaces silicon (Si) with an organic substrate/redistribution layer (RDL) as the interlayer. CoWoS-R uses InFO technology with RDL as the interlayer and provides services for interconnections between chiplets, especially in the heterogeneous integration of HBM (High Bandwidth Memory) and SoC. The RDL interlayer consists of polymers and copper traces, which have relatively high mechanical flexibility. This flexibility enhances the integrity of C4 joints and allows the new packaging to expand its size to meet more complex functional requirements.

CoWoS-L is an advanced packaging technology that uses chiplets and RDL as the interlayer (silicon bridge), combining the advantages of CoWoS-S and InFO technology, with flexible integration. CoWoS-L uses an interposer for chip-to-chip interconnection with LSI (Local Silicon Interconnect) chips, as well as RDL layers for power and signal transmission, starting from 1.5 times the reticle interposer size and 1 times SoC+4 times HBM cubes, and will expand forward to increase the envelope to a larger size to integrate more chips.

The main functions of CoWoS-L services include: first, LSI chips, which achieve high wiring density grain interconnection through multi-layer sub-micrometer copper wires. LSI chips can have various connection architectures in each product (e.g., SoC to SoC, SoC to chiplet, SoC to HBM, etc.), and can also be reused for multiple products. The corresponding metal types, layers, and pitches are consistent with CoWoS-S products. Second, the interposer-based interlayer has wide-pitch RDL layers on the front and back, with TIV (Through Interposer Vias) for signal and power transmission, providing low high-frequency signal loss during high-speed transmission. Third, it can integrate other components under the SoC chip, such as standalone IPD (Integrated Passive Devices), to support its signal communication with better PI/SI.