In late April, TSMC unveiled a new version of the 4nm process technology—N4C, scheduled for mass production in 2025. The core value of this process product is the reduction of costs. Although TSMC's main focus is on its leading process nodes, such as N3E and N2, a significant number of chips will continue to use the 5nm and 4nm processes in the coming years. N4C belongs to the company's 5nm process series, and to further reduce manufacturing costs, N4C has undergone some modifications, including the reconstruction of its standard cells and SRAM, changes to some design rules, and a reduction in the number of mask layers. Through these improvements, N4C can achieve a smaller chip size and reduce production complexity, thereby reducing chip costs by about 8.5%. In addition, N4C has the same wafer-level defect density rate as N4P, and due to the reduced chip area, N4C will achieve a higher yield. Higher yield means cost reduction.

TSMC stated that N4C provides customers with multiple options to find a better balance between cost-effectiveness and design workload.

In the second half of 2023, TSMC mass-produced 3nm process chips for customers, with the version being N3B, and its high cost is an issue. While further optimizing the 3nm process to reduce costs, TSMC also introduced N4C, fully reflecting the voice of customers who wish to use a more cost-effective FinFET process node.

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As advanced process technologies develop to 3nm, in the face of cost pressures, even major wafer foundries like TSMC have to find ways to cut costs and save on capital expenditures.

01

Financial reports and capital expenditures reflect cost pressures

TSMC's financial report for the third quarter of 2023 showed a quarterly revenue of 17.28 billion US dollars, an increase of 10.2% quarter-on-quarter, but a year-on-year decrease of 14.6%. Due to the poor overall revenue growth, TSMC has significantly reduced the capital expenditures that have been high in recent three years.

On April 18, 2024, TSMC released its financial report for the first quarter of 2024, in which the two most closely watched figures are revenue and gross margin. In this quarter, the company's revenue per wafer (equivalent to 12 inches) was about $6,228, a decrease of $407 quarter-on-quarter. Entering the first quarter, the decline in 3nm shipments lowered the average product price.In this quarter, TSMC's average fixed cost (depreciation and amortization) was approximately $1,671 per wafer, an increase of $73 per wafer compared to the previous quarter. The mass production of 3nm technology has driven up the total amount of depreciation and amortization, thereby increasing the unit fixed cost. The average variable cost (other manufacturing expenses) was about $1,252 per wafer, a decrease of $266 per wafer compared to the previous quarter.

In summary, the gross profit per wafer was $3,305, a decrease of $214 compared to the previous quarter. The unit price decreased by $407, while the unit cost decreased by $193.

Although the mass production of 3nm can drive up the company's average selling price (to over $6,000), which has a positive effect on the gross margin, the increase in costs on the cost side has affected the gross margin. Considering the company's gross margin guidance for the next quarter (51%-53%), its gross margin is expected to continue hovering at a low level. Additionally, the increase in electricity costs in the second quarter will also impact the company's gross margin.

From the financial report data, it can be seen that TSMC is facing significant cost pressures and must find ways to reduce costs.

Entering 2024, it was rumored that TSMC would increase its annual capital expenditure on the basis of the original plan (originally $28 billion to $32 billion), but at the first quarter financial report conference, the company stated that it would maintain the original capital expenditure plan unchanged. This is the result of TSMC's comprehensive consideration of the market situation for the whole year and the demand for cost control.

Not long ago, EUV lithography leader ASML released its financial report for the first quarter of 2024, with revenue of €5.29 billion, lower than market expectations (€5.47 billion). A significant reason for the decline in revenue this quarter is the obvious slowdown in shipments from TSMC and South Korean customers. EUV and ArFi are the main sources of the company's revenue, accounting for about 70% of its income. The year-on-year decline in revenue this quarter is mainly due to the slowdown in customer shipments of EUV and other products.

Overall, ASML's financial report is not very satisfactory, with both revenue and profit showing a clear decline. As a major customer, TSMC's reduced demand for EUV equipment directly leads to ASML's revenue decline. This also reflects TSMC's consideration for cost control from one side. To address costs, TSMC has focused on advanced packaging, as it can meet customer demand for advanced process chips while also saving costs. Relatively speaking, TSMC's demand for EUV lithography systems has weakened.

02

The High Cost of More Advanced Processes

4nm and 3nm are processes that have already been mass-produced, and the costs are already so high. The cost of the 2nm process, which is being prepared for mass production, will be even higher.Analysts at International Business Strategies (IBS) believe that the cost of 2nm chips will increase by about 50% compared to 3nm processors. IBS estimates that the cost of a 2nm production line with a capacity of approximately 50,000 wafers per month (WSPM) is around $28 billion, while a 3nm production line with similar capacity costs about $20 billion. A significant portion of the increased cost comes from the increased number of EUV lithography equipment, which will greatly increase the production cost per wafer and per chip. Only a few manufacturers, such as Apple, AMD, NVIDIA, and Qualcomm, can afford such high-cost chips.

IBS estimates that from 2025 to 2026, processing a single 12-inch wafer using TSMC's N2 process will cost Apple about $30,000, while the cost of a wafer based on the N3 process is around $20,000. With the increasing demand for AI processors, NVIDIA's share of TSMC's revenue may increase in 2024. The company has already booked TSMC's wafer foundry and CoWoS packaging capacity to ensure a stable supply of high-quality processors for AI. This year, AMD's share of TSMC's total revenue is expected to exceed 10%.

It is due to large customers like Apple, NVIDIA, and AMD placing orders that TSMC is able to make large-scale investments in the most advanced processes. Otherwise, it would be difficult to sustain the expensive production lines for processes like 3nm and 2nm. However, given the current situation, TSMC's forecast for the wafer foundry market in 2024 is relatively conservative, believing that previous estimates were overly optimistic (previously estimated at an annual industry growth of around 20%), and now it seems that the growth rate may only be around 10%. Under these circumstances, even with large customer orders, it is necessary to control costs and capital expenditures.

03

Samsung Benefits from TSMC's High Costs

As TSMC's biggest competitor, Samsung has found it difficult to break through in the existing competitive system. However, the moves by both companies to build factories on a large scale in the United States have provided opportunities for Samsung, as the cost of TSMC's 4nm and 5nm process chips manufactured in the United States is at least 20% to 30% higher compared to those in the Taiwan region.

It is reported that TSMC has begun discussing new wafer orders and negotiating new pricing with customers for its newly built wafer factory in the United States. TSMC is also building a wafer factory in Kumamoto, Japan, where it will produce 12nm, 16nm, 22nm, and 28nm chips. According to reports, the cost of chips produced at TSMC's Japanese factory will be 10% to 15% higher.The above news may be a boon for Samsung's foundry business, as it can offer contract manufacturing services for chips with the same process at a lower price than TSMC, potentially stealing some customer orders from TSMC.

Reports suggest that Samsung has received orders for 4nm chips from AMD and Google. AMD's next-generation CPU and GPU products, as well as Google's Tensor G3, can be manufactured using Samsung's improved 4nm process, which can achieve better energy efficiency and performance.

In 2023, Samsung reached an agreement with Ambarella to manufacture the latter's CV3-AD685 chip, which is used to process L2 to L4 level autonomous driving data. Additionally, Samsung also won the production order for Mobileye's ADAS chips, which were previously ordered from TSMC.

There are also media reports that Samsung will share in the large order for Tesla's next-generation Full Self-Driving (FSD) chips. It is said that the next-generation FSD chips will be produced using Samsung's 4nm process.

In previous years, Samsung was the contract manufacturer for the earlier version of Tesla's FSD chips. Later, Tesla chose TSMC as the main partner for producing HW 5.0 automotive chips because Samsung's 4nm process yield was far behind TSMC at that time. Industry observers have pointed out that over the past year, Samsung's 4nm yield has significantly improved, with little difference from TSMC, becoming a key factor in regaining Tesla's orders.

In May 2023, Samsung's Executive Chairman Lee Jae-yong met with Tesla CEO Musk to discuss ways to strengthen their technological alliance, which began to brew changes. Industry insiders revealed that during the meeting, Lee Jae-yong offered Musk an irresistible preferential contract price.

Faced with the improvement in Samsung's 4nm and 3nm process technology levels and yields, as well as price advantages, TSMC must do more on cost control, otherwise, its gross margin will decline significantly.

04

Tapping into the potential of advanced packaging

Since entering 2024, due to a significant decrease in iPhone orders, TSMC's 4nm process capacity utilization rate has been only around 70%.Currently, the reason why the 4nm process is not fully utilized is not due to a lack of orders, but rather because it is constrained by the capacity of advanced packaging CoWoS.

As a major consumer of AI chips, NVIDIA's new generation GPU B200 has a chip size that is twice as large as the H100, which will consume a significant amount of wafer capacity. If the packaging capacity (CoWoS) can keep up, there is a chance to fully utilize TSMC's 4nm capacity.

Whether TSMC's AI market share can rise rapidly and whether to increase capital expenditure, the determining factor is not the proportion of advanced processes, but is closely related to the capacity planning of CoWoS packaging.

Industry estimates suggest that TSMC's chip capacity will reach 320,000 wafers in 2024, and was originally estimated to be 450,000 wafers in 2025. Now, foreign capital has increased the estimate to 600,000 wafers per year, an increase of over 30%. It is evident that the status of advanced packaging has significantly improved and is now on par with advanced processes such as 4nm and 3nm.

In addition to chips with advanced processes below 5nm requiring advanced packaging like CoWoS, from a cost perspective, compared to traditional packaging, 3D packaging technology combined with advanced processes can reduce overall costs. Especially for wafer foundries of the scale of TSMC and Samsung, combining Chiplet and 3D packaging will become a lower-cost solution.

At present, large AI chips are mostly manufactured by TSMC, and looking at the future development trend, the number of transistors in AI chips will continue to increase. Since they are used in data centers and cloud computing, there is not much demand for size reduction, so future AI chips are likely to become larger and larger.

TSMC is developing AI chips with an area larger than AMD's Instinct MI300X and NVIDIA's B200 through CoWoS packaging technology, with a packaging area of 120mm x 120mm.

Here is a brief introduction to CoWoS (Chip On Wafer On Substrate), which is a 2.5D packaging technology from TSMC, combining CoW and oS. First, the chip is connected to the silicon wafer through the Chip on Wafer (CoW) packaging process, and then the CoW chip is connected to the substrate, integrating into CoWoS. The core of this technology is to stack different chips on the same silicon interposer to achieve interconnection between multiple chips. In the silicon interposer, TSMC uses micro-bumps (μBumps), Through-Silicon Vias (TSVs), and other technologies, replacing traditional wire bonding, for chip-to-chip connections, greatly increasing interconnection density and data transfer bandwidth. Depending on the different interposer materials used, TSMC classifies CoWoS packaging technology into three types: CoWoS-S (Silicon Interposer), CoWoS-R (RDL Interposer), and CoWoS-L (Local Silicon Interconnect and RDL Interposer).

TSMC's competitor, Samsung, is also developing advanced packaging technologies.

In order to compete with TSMC for AI large chip orders, Samsung has introduced the FO-PLP advanced packaging technology to attract customers.Samsung's DS division's Advanced Packaging (AVP) team is researching the use of FO-PLP technology for 2.5D packaging, which can integrate SoC and HBM onto a silicon interposer, forming a complete chip.

Unlike CoWoS, FO-PLP 2.5D is packaged on a square substrate, while CoWoS 2.5D uses a circular substrate. FO-PLP does not have the issue of edge substrate loss, offering higher production efficiency. However, the process is more complex as it requires the transfer of chips from wafers to square substrates.

If FO-PLP is successful, Samsung will be able to organically integrate its wafer foundry and memory businesses, providing a one-stop solution for AI chip customers, such as NVIDIA and AMD. If realized, Samsung will be able to offer differentiated services from TSMC, increasing its chances of securing more orders.

In addition to 2.5D, Samsung is also developing 3D packaging technology. It is reported that the company will use SAINT technology (Samsung Advanced Interconnect Technology) to integrate memory and processors required for high-performance chips in a smaller form factor.

Sources indicate that Samsung plans to introduce three types of SAINT technologies: SAINT S, for vertically stacking SRAM chips and CPUs; SAINT D, for vertical packaging of processors such as CPUs and GPUs with DRAM; and SAINT L, for stacking application processors.

It is reported that the SAINT S solution has passed validation tests, and insiders say that after further testing with customers, Samsung will launch commercial services next year.

In conclusion, advanced process nodes have reached the 3nm stage, with 2nm expected to enter mass production by 2025. Such advanced process technologies demand high standards for equipment, facilities, power, and technical personnel, with costs that are not affordable for ordinary wafer fabs, and the associated chip foundry prices are also beyond the reach of most IC design companies. Moreover, as processes continue to evolve, the costs of future 1nm and beyond technologies will be prohibitively high.

At present, even TSMC, which is hard to beat in the most advanced process technology market, cannot fully bear such high costs and needs to take measures to reduce them. Meanwhile, the gap between Samsung's advanced process technology and TSMC is narrowing, and with its cost advantage, TSMC faces significant pressure, and Samsung has the opportunity to win more orders.With Intel's entry and continuous enhancement of its influence in the wafer foundry market, it will exert more pressure on TSMC. If it does not control costs effectively, market share and gross margin will be difficult to maintain at the current level in the long term.